In order to minimize the space required by display devices, research into the development of various flat panel display devices such as LCD display devices, plasma display panels (PDP) and electro-luminescence displays (EL), has been undertaken to displace larger cathode-ray tube displays (CRT) as the most commonly used display devices. Particularly, in the case of LCD display devices, liquid crystal technology has been explored because the optical characteristics of liquid crystal material can be controlled in response to changes in electric fields applied thereto. As will be understood by those skilled in the art, a thin film transistor liquid crystal display (TFT LCD) typically uses a thin film transistor as a switching device and the electrical-optical effect of liquid crystal molecules to display data visually.
At present, the dominant methods for fabricating liquid crystal display devices and panels are typically methods based on amorphous silicon (a-Si) thin film transistor technologies. Using these technologies, high quality image displays of substantial size can be fabricated using low temperature processes. As will be understood by those skilled in the art, conventional LCD devices typically include a transparent (e.g., glass) substrate with an array of thin film transistors thereon, pixel electrodes, orthogonal gate and data lines, a color filter substrate and liquid crystal material between the transparent substrate and color filter substrate. The use of a-Si TFT technology typically also requires the use of separate peripheral integrated circuitry to drive the gates and sources (i.e., data inputs) of the TFTs in the array. In particular, gate driving signals from a gate driving integrated circuit are typically transmitted to the gate electrodes of TFTs in respective rows and data driving signals from a data driving integrated circuit are typically transmitted to the source electrodes of TFTs in respective columns. A display is typically composed of a TFT substrate in which a plurality of liquid crystal pixels are formed. Each pixel typically has at least one TFT and a pixel electrode coupled to the drain of the respective TFT. Accordingly, the application of a gate driving signal to the gate of a TFT will electrically connect the pixel electrode of a respective TFT to the data line connected thereto.
Referring to now to FIG. 1, a first conventional TFT LCD display device is illustrated comprising an array of TFT LCD display cells and gate and data driving ICs. In particular, a two-dimensional array of display cells are illustrated. Each cell comprises a TFT transistor having a source electrode connected to a data line (D1-Dn), a gate electrode connected to a gate line (G1-Gn) and a drain electrode connected to a respective pixel electrode internal to the cell. As will be understood by those skilled in the art, storage capacitors (Cst), liquid crystal capacitors (Clc) and gate-drain capacitors (Cgd) may be provided in each cell. As illustrated, the liquid crystal capacitors are connected in series between respective pixel electrodes and a common reference potential (Vcom) and the storage capacitors in each row of cells are connected in series between respective pixel electrodes and a next lower order gate line. For example, a storage capacitor in a first row of cells has first and second electrodes connected to a zeroth gate line GO and an internal pixel electrode, respectively. As illustrated by the device of FIG. 1, the zeroth gate line GO is not independently controlled but, instead, is electrically connected to the second gate line G2. Unfortunately, because the RC delay value associated with the zeroth gate line is unequal to the RC delay value associated with the first gate line G1 (and Gn-1 and Gn), the performance of the display device is deteriorated.
Referring now to FIG. 2, a second conventional TFT LCD display device is illustrated. This device of FIG. 2 is similar to the device of FIG. 1, however, the zeroth gate line GO is connected to a common reference potential (Vcom) instead of another gate line. Unfortunately, the RC delay value associated with the zeroth gate line GO can typically vary by about 10% from the RC delay values associated with the other gate lines, and this variation can also limit the performance of the display device.
Accordingly, notwithstanding the above described display devices, there still continues to be a need for improved display devices which are not limited by RC delay value variation.